According to a widespread architecture of the prior art, an electrically erasable and programmable memory, such as an electrically erasable programmable read only memory (EEPROM), comprises memory cells. Each memory cell includes a floating gate transistor and an access transistor of a metal oxide semiconductor (MOS) type and organized in a memory plane according to a matrix of n×m cells disposed in n rows (or lines) and m columns. Each memory cell is situated at the intersection of a word line and of a bit line. In such a structure of the prior art, a set of memory cells connected to the same word line within a row is called a physical page of the memory. The memory plane of such a memory is a set of pages.
FIG. 1 represents an example of an EEPROM memory part according to such an architecture. More precisely, this memory part comprises two columns and four rows, with which the four word lines WLi to WLi+3 are associated. In each of these rows, each column comprises eight bit lines (respectively BL0 to BL7 and BL8 to BL15) linked to eight memory cells. In this example represented, these eight cells disposed at each intersection of a column and of a row thus form a memory byte.
FIG. 2 more precisely represents such a memory byte. Each memory cell of this byte, such as the highlighted cell Ci0, comprises a floating gate transistor FGT and an access transistor AT as recalled hereinabove. The latter has its gate G connected to the word line WLi, its drain D connected to a bit line BL0, and its source S connected to the drain D of the floating gate transistor FGT. The latter has its source connected to a source line LS and its control gate G connected to a gate control line CGL0 by way of a gate control transistor CGT0, whose gate is linked to the word line WLi, whose drain D is connected to the gate selection line CGL0, and whose source S is connected to a potential common to the eight control gates of the floating gate transistors FGT. The gate selection line CGL0 extends over all the pages of the memory plane in a similar manner to the bit lines and links the gates of the floating gate transistors of each cell of the same column by way of the gate control transistor CGT. It should be noted that a source line LS extends in a similar manner to link the sources of each cell to the same source voltage, as explained previously.
In such a memory, each cell Cij may include a binary information item, which may be modified by a programming operation, which includes trapping electrical charge in the floating gate of the floating gate transistor FGT, or by an erasure operation, and which includes extracting charge from this floating gate. These operations of erasing or programming a memory cell, and more particularly, the floating gate transistor FGT of the cell, are done for example, by a tunnel effect (Fowler Nordheim effect). As a result, an erased floating gate transistor exhibits a greater threshold voltage than that of the programmed transistor. When a read voltage Vread chosen between these two threshold voltage values is applied to the control gate of such an floating gate transistor FGT, it remains off if it is in an erased state and on if it is in a programmed state, thereby making it possible to easily detect its state and to associate with it a binary value representing a stored data bit.
According to a routine scheme of the prior art, collective erasure of the floating gate transistors is achieved by applying a voltage of 15 to 20 V to the control gate of the floating gate transistors by way of the gate control transistor CGT0, while the source line is at 0 and the drain of the floating gate transistors is at a floating potential. The individual programming of floating gate transistors is achieved by applying the programming voltage Vpp to the drains of the floating gate transistors via the access transistors AT, while the control gate of the floating gate transistors is at 0 and the source line is at a floating potential.
FIG. 3 represents, more globally and schematically, a plane of such an EEPROM memory, comprising eight columns of 8 bits and 32 rows, i.e. a total of 2048 bits. Each word line WLi, not represented, of the memory plane is controlled by a voltage signal delivered by an output of a line decoder RDEC. Each column selection line CGLi receives a voltage from a column latch, not represented, in cooperation with a column decoder CDEC. Likewise, each bit line BLj is linked to a programming latch, not represented, and to a column decoder CDEC, so as to send it the signal for a desired operation. Finally, each source line LS is connected to a floating potential. In this figure, the memory plane thus comprises several pages disposed successively over the various rows, each page including the page Pi considered, therefore comprising eight bytes, including the two bytes Oi0 and Oi1highlighted by way of example, which are disposed at the intersections of this row i with columns 0 and 1, and are each associated with a gate control line CGL0, CGL1.
In practice, a programmable memory, such as this, is associated with a programming method which manages write commands so as to trigger programming cycles, a prior step of which comprises the definition of a starting address for writing a certain data item to the memory. This address includes the definition of the write row concerned, as well as the column where writing begins. Thereafter, another prior step comprises the activation of all the latches of bit lines whose bits are involved in the write so as thereafter to undertake the programming cycle. During the latter, all the desired latches of the memory have been activated. Thereafter, each programming cycle firstly comprises a cycle of erasing all the bits of the bytes involved in the write and then a write cycle as such in which the programming potential Vpp of the memory is brought to its programming value, thereby ultimately allowing the simultaneous and automatic programming of all the bits that take the value “1”, such as are defined by the data to be stored.
In practice, such a write cycle is implemented by commencing the writing of the data to be stored at the first column of a chosen row, and the size of the data to be stored remains less than or equal to the size of a page. However, if the beginning of programming is initiated on an intermediate column of the memory plane, and if the end of the row is reached, that is to say column 7 is completely written, returning to the example related to FIG. 3, the programming then uses column 0 and so on and so forth over the same row. All the data are therefore written on the same page Pi corresponding to the single row i addressed by the write cycle. This approach thus presents the drawback of not systematically positioning all the data in an increasing order of the addresses of the bits of the memory, thereby greatly complicating the organization and utilization of these stored data.
To alleviate this drawback, provisions may be made so that the programming cycles for an electronic memory do not overstep the end of a row during a programming cycle, which uses for this purpose preferably the beginning of a row of the memory plane as initial storage address. This writing constraint represents, however, a lack of flexibility in the utilization of an electrically programmable memory. Thus, it may be desirable to improve the programming of an electrically programmable memory which makes it possible to deal with the drawback mentioned hereinabove.